


module R_type(
    input [2:0] funct3,
    input bit_th,
    input signed [31:0] in1, in2,  //����signed
    output reg [31:0] out
);
    wire [31:0] tmp1;
    wire [31:0] tmp2;
    assign tmp1 = in1;
    assign tmp2 = in2;

always @(*) begin
    case(funct3)
        3'b000: begin 
	        if(bit_th == 0) out = in1 + in2; 
	        else out = in1 - in2;
	    end
        3'b001: out = in1 << in2[4:0];
        3'b010: out = (in1 < in2) ? 1 : 0;
        3'b011: out = (tmp1<tmp2) ? 1 : 0;  //($unsigned(in1) < $unsigned(in2)) ? 1 : 0;
        3'b100: out = in1 ^ in2;
        3'b101: begin
	        if(bit_th == 0) out = in1 >> in2[4:0]; 
	        else out = in1 >>> in2[4:0];
	    end
        3'b110: out = in1 | in2;
        3'b111: out = in1 & in2;
        default: out = 32'b0;
    endcase
end

endmodule

